Modern semiconductor devices such as, for example, integrated circuit (IC) devices or chips may typically be manufactured using wafers. A wafer may typically include one or a plurality of integrally formed dies, and one or more separation line regions (for example, kerf regions or scribe line regions), along which the wafer may be diced to individualize the dies or chips. Sometimes, one or more of the separation line regions may be at least partially filled with one or more electrical structures such as PCM (process control monitoring) structures or other testlines or metrology structures, and metallization areas or pads (e.g. testline pads) may be provided in the separation line regions to enable electrical contact to those electrical structures (e.g testlines).
Dicing the wafer may commonly be carried out mechanically by means of cutting, though other dicing methods have recently emerged, such as laser stealth dicing (sometimes simply referred to as stealth dicing or laser dicing). Laser stealth dicing may include a two-stage process in which defect regions may be firstly introduced into the wafer by scanning a laser beam (typically, an infrared (IR) laser beam) along the separation line region or regions and secondly an underlying elastic carrier, e.g. a carrier membrane or tape, may be expanded to induce fracture of the wafer at the separation line region or regions.
Laser stealth dicing may be seen as a separation or dicing method which may achieve high quality sidewalls in the wafer material (e.g. silicon). Up to now, one restriction of laser stealth dicing, though, may be seen in that laser stealth dicing may not be able to separate stacks of thick metal layers. For example, it may be difficult to well separate a thick last metal of PCM or testline pads in separation line regions of the wafer.
Laser stealth dicing may generally be very cost-efficient for small chips (e.g. chips having an area in the range from about 3 mm2 to about 5 mm2) and thin wafer thicknesses. For small chips, testlines may typically be placed in drop-in areas of the wafer replacing chips. Thus, a cost-efficient small separation line region (for example having a width in the range of about 15-20 μm), and/or a separation line region free of metal plates may be obtained, which may provide good conditions for stealth dicing.
On the other hand, for large chips (e.g. chips having an area larger than 5 mm2), it may generally be more efficient to use wafers, in which testlines and corresponding pads are placed in the separation line region or regions. For these chips, stealth dicing may generally be highly efficient for thin wafer thicknesses, for example wafer thicknesses lower than 150 μm, where stealth dicing may, for example, require only one or two laser scans with a scanning speed of more than 300 mm/s, whereas mechanical dicing may typically be done with a step cut at a speed of around 50 mm/s or even slower. In the latter case, it may be desirable that the stealth dicing may be able to separate the pads (e.g. testline pads) in the separation line region or regions, for example pads including thick metal layers.